Electronic circuit designs can be constructed, simulated, debugged, and translated into electronic hardware using a High Level Modeling System (HLMS). Typically, an HLMS is implemented as a software-based design tool which provides blocks that can be combined to build an electronic circuit. A block and a module refer to high level software constructs that represent a particular circuit function, such as multiplexing, addition, multiplication, or the like. Blocks and modules may have ports that can produce and consume signals, and may be arranged within the HLMS to form a circuit and/or system. Communication among the constructs can be represented by wires, or signals, that graphically link the constructs. The design may be simulated within the HLMS once it is constructed. Some HLMS tools can generate a hardware implementation from the block and/or module representation of the circuit design. For example, an HLMS may generate the bitstream necessary to program a programmable logic device (PLD) or generate the hardware description language (HDL) files necessary to specify the hardware design.
PLDs are a well-known type of integrated circuit. A PLD can be programmed by a user to perform specified logic functions. There are different types of PLDs, such as programmable logic arrays (PLAs), complex programmable logic devices (CPLDs), and field programmable gate arrays (FPGAs). An FPGA, for example, typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure can be programmed by loading a stream of configuration data, referred to as a bitstream, into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. An FPGA may also include various dedicated logic circuits, such as memories, microprocessors, digital clock managers (DCMs), and input/output (I/O) transceivers.
One example of an HLMS is System Generator for DSP™, available from Xilinx, Inc. of San Jose, Calif. System Generator for DSP™ is a system level modeling tool that facilitates FPGA hardware design. System Generator for DSP™ provides a wide range of blocks that can be automatically compiled into a design suitable for an FPGA. Among these blocks are high level abstractions that implement complex functions, including digital signal processing as well as communication and control logic. In addition, access to underlying FPGA resources can be provided through low level block abstractions that facilitate the construction of highly efficient FPGA designs. (Xilinx and System Generator for DSP are trademarks of Xilinx, Inc. in the United States, other countries, or both).
Some modern FPGAs, and associated development tools, support a feature known as dynamic partial reconfiguration. Dynamic partial reconfiguration refers to the ability of a region of an FPGA to be reprogrammed to implement a plurality of different circuits while other regions of the FPGA continue to operate unchanged and uninterrupted. Typically, dynamic partial reconfiguration is performed to replace one function within the FPGA with a different function or circuit. In other words, the logic of the dynamically reconfigurable region of the FPGA is replaced with different logic, while the other regions of the FPGA remain unchanged. The new, or different, logic in the dynamically reconfigurable region of the FPGA may be entirely different from the logic that was replaced. There can be 2, 3, or more different circuit alternatives, or functions, that can be implemented within the dynamically reconfigurable region of the FPGA.
The dynamically reconfigurable region of the FPGA must continue to properly connect with other regions of the FPGA when the circuit implemented in that region is replaced with another circuit. One mechanism that has been used to ensure proper linkage between the dynamically reconfigurable regions of an FPGA and other regions is the bus macro. In general, a bus macro provides a mechanism for creating a physical connection on the FPGA that ensures that inputs and outputs of a dynamically reconfigurable region always properly connect to other regions of the FPGA.
Bus macros, however, can be complex to use and incorporate into a circuit design. Often, a circuit design includes hundreds, or possibly thousands, of connections between dynamically reconfigurable portions of the circuit design and the other portions. A bus macro is needed for each such connection. Each instance of a bus macro must be manually wired, or inserted, into the programmatic description of the circuit design. Another disadvantage of bus macros is that the inclusion of a bus macro introduces additional delay into that circuit design. Moreover, bus macro implementation requires additional resources beyond those needed to implement the original circuit design, thereby leaving fewer resources available for user logic.